With the increasing complexity that is being introduced to engineered systems, the literature suggests that verification may benefit from theoretical foundations. In practice and in teaching of system engineering (SE), we typically define a verification model (simulation, test article, etc.) under the assumption that the model is a valid representation of the system design. Is this assumption always true? In this article, we explore the use of system theoretic morphisms to mathematically characterize the validity of representativeness between verification models and corresponding system design.